完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jung, Pei-Yu | en_US |
dc.contributor.author | Panda, Debashis | en_US |
dc.contributor.author | Chandrasekaran, Sridhar | en_US |
dc.contributor.author | Rajasekaran, Sailesh | en_US |
dc.contributor.author | Tseng, Tseung-Yuen | en_US |
dc.date.accessioned | 2020-03-02T03:23:33Z | - |
dc.date.available | 2020-03-02T03:23:33Z | - |
dc.date.issued | 2020-01-01 | en_US |
dc.identifier.issn | 2168-6734 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/JEDS.2020.2966799 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/153826 | - |
dc.description.abstract | To move towards a new generation powerful computing system, brain-inspired neuromorphic computing is expected to transform the architecture of the conventional computer, where memristors are considered to be potential solutions for synapses part. We propose and demonstrate a novel approach to achieve remarkable improvement of analog switching linearity in TaN/Ta/TaOx/Al2O3/Pt/Si memristors by varying Al2O3 layer thickness. Presence of the Al2O3 layer is confirmed from the Auger Electron Spectroscopy study. Good analog switching ratio of about 100x and superior switching uniformity are observed for the 1 nm Al2O3 based device. Multilevel capability of the memristive devices is also explored for prospective use as a synapse. More than 104 and 4 x 10(4) cycles nondegradable dc and ac endurances, respectively, alongwith 10(4) second retention are achieved for the optimized device. Improved linearities of 2.41 and -2.77 for potentiation and depression, respectively are obtained for such 1 nm Al2O3-based devices. The property of gradual resistance changed by pulse amplitudes confirms that the TaOx memristors can be potentially used as an electronic synapse. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Memristors | en_US |
dc.subject | synapse | en_US |
dc.subject | neuromorphic computing | en_US |
dc.title | Enhanced Switching Properties in TaOx Memristors Using Diffusion Limiting Layer for Synaptic Learning | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/JEDS.2020.2966799 | en_US |
dc.identifier.journal | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | en_US |
dc.citation.volume | 8 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 110 | en_US |
dc.citation.epage | 115 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000510901100002 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |