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dc.contributor.authorYou, Wei-Xiangen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorHu, Chenmingen_US
dc.date.accessioned2020-05-05T00:02:21Z-
dc.date.available2020-05-05T00:02:21Z-
dc.date.issued2020-01-01en_US
dc.identifier.issn2168-6734en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JEDS.2020.2972319en_US
dc.identifier.urihttp://hdl.handle.net/11536/154163-
dc.description.abstractThis paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.en_US
dc.language.isoen_USen_US
dc.subjectFerroelectric field-effect transistor FETen_US
dc.subjectnegative-capacitance FET (NCFET)en_US
dc.subjectFinFETen_US
dc.subjectnonvolatile SRAM (nvSRAM)en_US
dc.subjectnonvolatile memoryen_US
dc.titleA New 8T Hybrid Nonvolatile SRAM With Ferroelectric FETen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JEDS.2020.2972319en_US
dc.identifier.journalIEEE JOURNAL OF THE ELECTRON DEVICES SOCIETYen_US
dc.citation.volume8en_US
dc.citation.issue1en_US
dc.citation.spage171en_US
dc.citation.epage175en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department國際半導體學院zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentInternational College of Semiconductor Technologyen_US
dc.identifier.wosnumberWOS:000526721100004en_US
dc.citation.woscount0en_US
Appears in Collections:Articles