標題: Logical Effort Models with Voltage and Temperature Extensions in Super-/Near-/Sub-threshold Regions
作者: Chang, Ming-Hung
Hsieh, Chung-Ying
Chen, Mei-Wei
Hwang, Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2011
摘要: The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold logical effort models are proposed to eliminate delay estimation error caused by voltage and temperature variations. These models establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply voltage 0.1 similar to 1V and full temperature -50 similar to 125 degrees C range into account. The simulation results are using UMC 90-nm, PTM 65-, 45-and 32-nm bulk CMOS technologies, respectively. The average absolute error among the three regions are only 6.01%, 4.12%, 8.01% and 6.55% for UMC 90-nm, PTM 65-, 45-and 32-nm technology, respectively. Proposed models extend the original high performance circuits design in super-threshold region to low power circuit design in near-threshold and sub-threshold regions. They are useful for future green electronics applications.
URI: http://hdl.handle.net/11536/15480
ISBN: 978-1-4244-8499-7
期刊: 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
起始頁: 213
結束頁: 216
Appears in Collections:Conferences Paper