標題: A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance
作者: Hsieh, E. R.
Chang, H. Y.
Chung, Steve S.
Chen, T. P.
Huang, S. A.
Chen, T. J.
Cheng, Osbert
Wong, S. Simon
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-Jan-2019
摘要: In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (>10(12)). much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's V-th, to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. 1kb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64x64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.
URI: http://hdl.handle.net/11536/155274
ISBN: 978-4-86348-719-2; 978-4-86348-717-8
期刊: 2019 SYMPOSIUM ON VLSI TECHNOLOGY
起始頁: 0
結束頁: 0
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