ESD Improvements on Power N-Channel LDMOS Devices by the Composite Structure of Super Junctions Integrated With SCRs in the Drain Side

Abstract

This paper studies a composite power n-channel lateral-diffused MOSFET device with a super junction (SJ) and parasitic silicon-controlled rectifier structure (nLDMOS-SJ-SCR) in the drain side, which can be used for electrostatic discharge (ESD) and latch-up (LU) reliability enhancements of 60-V power electronics. For ESD and LU protection considerations, the drain side with an SJ structure integrated with p-n-p- and n-p-n-arranged types of nLDMOS-SCR transistors is demonstrated. According to the experimental data, the layout of the SJ structure in the drain side has positive effects on ESD and LU capabilities. The layout type of nLDMOS-SJ with a pillar width W = 9 mu m has the highest secondary breakdown current (I-t2) values; the ESD (LU) improvement was 46.3% (13.3%) compared with the nLDMOS reference sample. Meanwhile, an nLDMOS-SJ with a pillar width W = 27 mu m has the highest figure of merit (FOM) value. By contrast, an embedded p-n-p-(n-p-n-)arranged type SCR structure was added into the drain side once again. Initially, it has a positive (negative) effect on the ESD reliability. Furthermore, the ESD (figure of merit; FOM) improvement was 37.9% (13.72%) of the corresponding nLDMOS-SJ device for nLDMOS-SJ-SCR (p-n-p) with W = 27 mu m. Overall, an nLDMOS-SJ device integrated with the p-n-p-arranged-type SCR in the drain side is a favorable choice for ESD and LU improvements.