標題: Interface Defect Shielding of Electron Trapping in a-InGaZnO Thin Film Transistors
作者: Lin, Chih-Chih
Tai, Mao-Chou
Chang, Ting-Chang
Tsao, Yu-Ching
Wang, Yu-Xuan
Tsai, Yu-Lin
Tu, Hong-Yi
Lu, I-Nien
Tsai, Tsung-Ming
Huang, Jen-Wei
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Stress;Logic gates;Thin film transistors;Threshold voltage;Reliability;Mathematical model;Amorphous InGaZnO (a-IGZO);channel thickness;charge trapping;interface defects
公開日期: 1-Sep-2020
摘要: In this work, an abnormal lowering of subthreshold swing (SS) after self-heating stress in a device with thick channel is observed. A model of interface defect shielding is proposed, based on electron trapping at the channel/gate insulator interface. The phenomenon is discussed systematically through the band diagram and extractions of the field effective mobility. Results suggest that a depletion region appears after electron trapping at the front channel, which then prevents the carriers from reaching the interface defects. Therefore, an abnormal superior electrical performance after stress is observed. Finally, a dual gate amorphous InGaZnO (a-IGZO) thin film transistor (TFT) is used to clarify the phenomenon. Results from different top gate bias voltage confirms the bulk accumulation and better gate control.
URI: http://dx.doi.org/10.1109/TED.2020.3011386
http://hdl.handle.net/11536/155440
ISSN: 0018-9383
DOI: 10.1109/TED.2020.3011386
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 67
Issue: 9
起始頁: 3645
結束頁: 3649
Appears in Collections:Articles