Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_Line

Abstract

A 0.45 V 28-nm 32 -Kb SRAM with multi-powersupply low-power circuits, such as a cross-point 5T with built-in Y_line, gate-boosted drivers and adaptive tracking circuits, demonstrates a sub-ns access time and sub mW/GHz power dissipation. The 5T circuits are feasible to reduce the power of a 6T 32-Kb core to about 30% with quite the same sub-ns access time. The performance evaluation also indicates the new bit cell and array architecture open the door to the sub-ns access time and sub mW/GHz in sub-0.5 V multi-Mb era.