Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor

Abstract

Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.