完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, Hung-Bin | en_US |
dc.contributor.author | Wu, Yung-Chun | en_US |
dc.contributor.author | Chen, Lun-Chun | en_US |
dc.contributor.author | Chiang, Ji-Hong | en_US |
dc.contributor.author | Yang, Chao-Kan | en_US |
dc.contributor.author | Chang, Chun-Yen | en_US |
dc.date.accessioned | 2014-12-08T15:22:45Z | - |
dc.date.available | 2014-12-08T15:22:45Z | - |
dc.date.issued | 2012-04-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/16081 | - |
dc.description.abstract | This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Nanocrystal (NC) | en_US |
dc.subject | nonvolatile memory (NVM) | en_US |
dc.subject | thin-film transistor (TFT) | en_US |
dc.title | High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer | en_US |
dc.type | Article | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 33 | en_US |
dc.citation.issue | 4 | en_US |
dc.citation.epage | 537 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000302232900024 | - |
dc.citation.woscount | 5 | - |
顯示於類別: | 期刊論文 |