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dc.contributor.authorChen, Hung-Binen_US
dc.contributor.authorWu, Yung-Chunen_US
dc.contributor.authorChen, Lun-Chunen_US
dc.contributor.authorChiang, Ji-Hongen_US
dc.contributor.authorYang, Chao-Kanen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.date.accessioned2014-12-08T15:22:45Z-
dc.date.available2014-12-08T15:22:45Z-
dc.date.issued2012-04-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://hdl.handle.net/11536/16081-
dc.description.abstractThis letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.en_US
dc.language.isoen_USen_US
dc.subjectNanocrystal (NC)en_US
dc.subjectnonvolatile memory (NVM)en_US
dc.subjectthin-film transistor (TFT)en_US
dc.titleHigh-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layeren_US
dc.typeArticleen_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume33en_US
dc.citation.issue4en_US
dc.citation.epage537en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000302232900024-
dc.citation.woscount5-
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