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dc.contributor.authorHong, Hao-Chiaoen_US
dc.date.accessioned2014-12-08T15:22:46Z-
dc.date.available2014-12-08T15:22:46Z-
dc.date.issued2012-04-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://hdl.handle.net/11536/16092-
dc.description.abstractThis paper proposes a static linear behavior (SLB) analog fault model for switched-capacitor (SC) circuits. The SC circuits under test (CUT) are divided into functional macros including the operational amplifiers, the capacitors, and the switches. Each macro has specified design parameters from the design's perspectives. These design parameters constitute a parameter set which determines the practical transfer function of the CUT. The SLB fault model defines that a CUT is faulty if its parameter set results in transfer functions whose frequency responses are out of the design specification. We analyzed the fault effects of the macros and derived their faulty signal-flow graph models with which the faulty transfer function templates of the CUT can be automatically generated. Based on the templates, we proposed a test procedure that can estimate all the parameters in the parameter set so as to test the CUT with multiple faults. Different from conventional single fault assumption, the proposed SLB fault model covers concurrent multiple parametric faults and catastrophic faults. In addition, it does not need to conduct fault simulations before test as conventional analog fault models do. As a result, it addresses the impractically long fault simulation time issue. A fully-differential low-pass SC biquad filter was adopted as an example to demonstrate how to design and use efficient multitone tests to test for the parameter set. The multitone test results acquired during the test procedure also reveal the distortion and noise performance of the CUT though the SLB fault model does not include them.en_US
dc.language.isoen_USen_US
dc.subjectAnalog fault modelen_US
dc.subjectmixed-signal testingen_US
dc.subjectparametric faultsen_US
dc.subjectswitched-capacitor (SC)en_US
dc.titleA Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuitsen_US
dc.typeArticleen_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume31en_US
dc.citation.issue4en_US
dc.citation.epage597en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000302177200012-
dc.citation.woscount5-
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