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dc.contributor.authorKuo, Chia-Haoen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorLee, I-Cheen_US
dc.contributor.authorCheng, Huang-Chungen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2014-12-08T15:23:36Z-
dc.date.available2014-12-08T15:23:36Z-
dc.date.issued2012-06-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://hdl.handle.net/11536/16497-
dc.description.abstractA novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters.en_US
dc.language.isoen_USen_US
dc.subjectCMOS inverteren_US
dc.subjectpoly-Sien_US
dc.subjectsystem-on-panel (SoP)en_US
dc.subjectthin-film transistor (TFT)en_US
dc.titleA Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channelsen_US
dc.typeArticleen_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume33en_US
dc.citation.issue6en_US
dc.citation.epage833en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000305835000031-
dc.citation.woscount2-
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