標題: Design migration from peripheral ASIC design to area-I/O flip-chip design by chip I/O planning and legalization
作者: Chang, Chia-Yi
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: area-array flip-chip;design migration;input/output (I/O) planning and legalization
公開日期: 1-Jan-2008
摘要: Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.
URI: http://dx.doi.org/10.1109/TVLSI.2007.912202
http://hdl.handle.net/11536/164
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2007.912202
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 16
Issue: 1
起始頁: 108
結束頁: 112
Appears in Collections:Conferences Paper


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