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dc.contributor.authorYang, Hao-Ien_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:23:36Z-
dc.date.available2014-12-08T15:23:36Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-3827-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/16500-
dc.description.abstractThe threshold voltage (V(T)) drift induced by Negative Bias Temperature Instability (NBTI) weakens PFETs, while Positive Bias Temperature Instability (PBTI) weakens NFETs fabricated with high-k metal-gate, respectively. These long-term V(T) drifts degrade SRAM cell stability, margin and performance, and may lead to functional failure over the life of usage. Additionally, most state-of-the-art SRAMs are designed with power-gating structures to reduce leakage currents in Standby or Sleep mode, and the power switches suffer NBTI or PBTI stress/degradation as well. This paper presents a comprehensive analysis on the impacts of NBTI and PBTI on power-gated SRAM arrays with high-k metal-gate devices. NBTI/PBTI tolerant sense amplifier structures are also discussed.en_US
dc.language.isoen_USen_US
dc.titleImpacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devicesen_US
dc.typeProceedings Paperen_US
dc.identifier.journalISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5en_US
dc.citation.spage377en_US
dc.citation.epage380en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000275929800095-
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