標題: | POSA: Power-State-Aware Buffered Tree Construction |
作者: | Jiang, Iris Hui-Ru Wu, Ming-Hua 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2009 |
摘要: | Buffering without considering power states in multiple supply voltage designs may result in infeasible signals. POSA is the first work to handle this issue. Our buffered tree guarantees feasibility all the times, even when some parts of the design shut down. This feature is one of the key techniques to fulfill power-aware design methodology. |
URI: | http://hdl.handle.net/11536/16555 |
ISBN: | 978-1-4244-3827-3 |
期刊: | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
起始頁: | 787 |
結束頁: | 787 |
顯示於類別: | 會議論文 |