In-Plane Gate Transistors With a 40-mu m-Wide Channel Width

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DC 欄位	值	語言
dc.contributor.author	Chung, Tung-Hsun	en_US
dc.contributor.author	Lin, Wei-Hsun	en_US
dc.contributor.author	Chao, Yi-Kai	en_US
dc.contributor.author	Chang, Shu-Wei	en_US
dc.contributor.author	Lin, Shih-Yen	en_US
dc.date.accessioned	2014-12-08T15:23:48Z	-
dc.date.available	2014-12-08T15:23:48Z	-
dc.date.issued	2012-08-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://hdl.handle.net/11536/16603	-
dc.description.abstract	An in-plane gate transistor with a GaAs/AlGaAs 2-D electron-gas channel about 40 mu m in width is investigated. The saturation region and the drain current modulation at different gate bias voltages are observed despite the wide channel. The surface-induced channel depletion is suggested as the main mechanism for the turn-off of the drain current at -10 V gate bias.	en_US
dc.language.iso	en_US	en_US
dc.subject	In-plane gate transistors (IPGTs)	en_US
dc.subject	2-D electron gas (2DEG)	en_US
dc.title	In-Plane Gate Transistors With a 40-mu m-Wide Channel Width	en_US
dc.type	Article	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	33	en_US
dc.citation.issue	8	en_US
dc.citation.epage	1129	en_US
dc.contributor.department	光電工程學系	zh_TW
dc.contributor.department	Department of Photonics	en_US
dc.identifier.wosnumber	WOS:000306923700011	-
dc.citation.woscount	3	-
顯示於類別：	期刊論文

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