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dc.contributor.authorYen, Shao-Weien_US
dc.contributor.authorHung, Shiang-Yuen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:24:02Z-
dc.date.available2014-12-08T15:24:02Z-
dc.date.issued2012-09-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://hdl.handle.net/11536/16712-
dc.description.abstract"An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s mm(2) and energy efficiency of 62.4 pJ/b, respectively."en_US
dc.language.isoen_USen_US
dc.subjectIEEE 802.15.3cen_US
dc.subjectlow-density parity-check (LDPC) codesen_US
dc.subjectrow-based layered schedulingen_US
dc.titleA 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applicationsen_US
dc.typeArticleen_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume47en_US
dc.citation.issue9en_US
dc.citation.epage2246en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000308007900025-
dc.citation.woscount10-
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