16.9-mW 33.7-dB Gain mm Wave Receiver Front-End in 65 nm CMOS

Abstract

This work presents a low power receiver front-end design for the 77 GHz radar application. The theoretical maximum achievable gains in the LNA and the mixer are derived by using energy conservation principle. It is shown that the maximum gain can be increased by raising the impedance ratio between stages. The impedance transformation is able to provide high passive gain without any power consumption. Moreover, the quality of the passive components plays a critical role to approach the maximum gain condition. Accordingly a low power receiver front-end is designed in 65 nm CMOS. The measured results show the highest gain of 33.7 dB at 73 GHz with 3 dB bandwidth from 67 GHz to 75 GHz. The input return loss, P1dB, IIP3, and NF at IF frequency of 8 MHz, are 16.4 dB, -32 dBm, -19 dBm, and 12.2 dB, respectively. The power consumption is only 16.9 mW from a 1 V supply. To the best of our knowledge, this work shows the highest gain while consumes the lowest power as compared to the prior works.