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dc.contributor.authorTasi, Meng-Jaien_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.contributor.authorJou, Jing-Yangen_US
dc.contributor.authorWu, Meng-Chenen_US
dc.date.accessioned2014-12-08T15:24:50Z-
dc.date.available2014-12-08T15:24:50Z-
dc.date.issued2009en_US
dc.identifier.isbn978-0-7695-3598-2en_US
dc.identifier.issn1093-0167en_US
dc.identifier.urihttp://hdl.handle.net/11536/17273-
dc.identifier.urihttp://dx.doi.org/10.1109/VTS.2009.31en_US
dc.description.abstractThe fault diagnosis has become an increasing portion of today's IC-design cycle and significantly determines product's time-to-market. However, the failure behaviors from the defective chips may not be fully represented by the single fault model. In this paper, we propose a fault-diagnosis framework targeting multiple stuck-at faults. This framework first reports a minimal suspect region, in which all real faults are topologically covered. Next, a proposed ranking method is applied to sieve out the real faults from the candidates within the suspect region. The experimental results show that the proposed diagnosis framework can effectively locate the multiple stuck-at faults within a neighborhood, which may generate erroneous signals cancelling one another and are difficult to be diagnosed based on a single-fault-model method.en_US
dc.language.isoen_USen_US
dc.titleMultiple-Fault Diagnosis Using Faulty-Region Identificationen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/VTS.2009.31en_US
dc.identifier.journal2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGSen_US
dc.citation.spage123en_US
dc.citation.epage128en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000271941000021-
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