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dc.contributor.authorLiu, Tsu-Mingen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:24:57Z-
dc.date.available2014-12-08T15:24:57Z-
dc.date.issued2006en_US
dc.identifier.isbn1-4244-0179-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17320-
dc.description.abstractMemory storage is crucial power factor in H.264/AVC video decoding system. In this paper, we exploit three-level of memory hierarchy to break the data dependency and reduce the number of access for external memory. further, we apply line-pixel-lookahead (LPL) scheme to make a compromise between power consumption and internal memory cost. Experimental results prove that about 50% of memory power reduction can be achieved as compared to comparable decoders without exploiting memory hierarchy [1][2].en_US
dc.language.isoen_USen_US
dc.titleMemory-hierarchy-based power reduction for H.264/AVC video decoderen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage247en_US
dc.citation.epage250en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239709500064-
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