標題: | A 52mW 1200MIPS compact DSP for multi-core media SoC |
作者: | Ou, Shih-Hao Lin, Tay-Jyi Huang, Chao-Wei Kuo, Yu-Ting Chao, Chie-Min Liu, Chih-Wei Jen, Chein-Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2006 |
摘要: | This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power. |
URI: | http://hdl.handle.net/11536/17335 |
ISBN: | 0-7803-9451-8 |
期刊: | ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS |
起始頁: | 118 |
結束頁: | 119 |
Appears in Collections: | Conferences Paper |