完整後設資料紀錄
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dc.contributor.authorKao, Yao-Huangen_US
dc.contributor.authorHsieh, Yi-Binen_US
dc.date.accessioned2014-12-08T15:25:05Z-
dc.date.available2014-12-08T15:25:05Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0386-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17454-
dc.description.abstractA spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (EA) modulator is presented in this paper. The proposed EA modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. The proposed SSCG has been fabricated in TSMC 0.35-um double-poly quadruple-metal CMOS process with output frequency of 300MHz. The active area is 0.63x4.62 mm(2) and the power consumption is 17.5mW.en_US
dc.language.isoen_USen_US
dc.subjectPLLen_US
dc.subjectspread spectrumen_US
dc.subjectsigma-delta modulatoren_US
dc.titleA wide input-range Sigma Delta modulator for applications to spread-spectrum clock generatoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE Asia Pacific Conference on Circuits and Systemsen_US
dc.citation.spage530en_US
dc.citation.epage533en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000246793200133-
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