完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Kao, Yao-Huang | en_US |
dc.contributor.author | Hsieh, Yi-Bin | en_US |
dc.date.accessioned | 2014-12-08T15:25:05Z | - |
dc.date.available | 2014-12-08T15:25:05Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0386-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17454 | - |
dc.description.abstract | A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (EA) modulator is presented in this paper. The proposed EA modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. The proposed SSCG has been fabricated in TSMC 0.35-um double-poly quadruple-metal CMOS process with output frequency of 300MHz. The active area is 0.63x4.62 mm(2) and the power consumption is 17.5mW. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | PLL | en_US |
dc.subject | spread spectrum | en_US |
dc.subject | sigma-delta modulator | en_US |
dc.title | A wide input-range Sigma Delta modulator for applications to spread-spectrum clock generator | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 IEEE Asia Pacific Conference on Circuits and Systems | en_US |
dc.citation.spage | 530 | en_US |
dc.citation.epage | 533 | en_US |
dc.contributor.department | 傳播研究所 | zh_TW |
dc.contributor.department | Institute of Communication Studies | en_US |
dc.identifier.wosnumber | WOS:000246793200133 | - |
顯示於類別: | 會議論文 |