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dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorChang, Wei-Kengen_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:25:05Z-
dc.date.available2014-12-08T15:25:05Z-
dc.date.issued2006en_US
dc.identifier.isbn978-1-4244-0386-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/17463-
dc.description.abstractA pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bits are pre-compared in advance through the pre-comparison circuit. With the pre-comparison scheme, it will reduce the discharging time and power consumption when the match line is mismatch. The size of the CAM array is about 32 words, and each word has 32bits. The proposed pre-comparison NOR-type 10T CAM can achieve 22.8% power reduction for the 4bits pre-comparison circuit All the simulation results are based on TSMC 0.13um CMOS technology and the clock frequency is 500MHz.en_US
dc.language.isoen_USen_US
dc.titleLow power pre-comparison scheme for NOR-type 10T content addressable memoryen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 IEEE Asia Pacific Conference on Circuits and Systemsen_US
dc.citation.spage1301en_US
dc.citation.epage1304en_US
dc.contributor.department友訊交大聯合研發中心zh_TW
dc.contributor.departmentD Link NCTU Joint Res Ctren_US
dc.identifier.wosnumberWOS:000246793200325-
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