完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Po-Tsang | en_US |
dc.contributor.author | Chang, Wei-Keng | en_US |
dc.contributor.author | Hwang, Wei | en_US |
dc.date.accessioned | 2014-12-08T15:25:05Z | - |
dc.date.available | 2014-12-08T15:25:05Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 978-1-4244-0386-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17463 | - |
dc.description.abstract | A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bits are pre-compared in advance through the pre-comparison circuit. With the pre-comparison scheme, it will reduce the discharging time and power consumption when the match line is mismatch. The size of the CAM array is about 32 words, and each word has 32bits. The proposed pre-comparison NOR-type 10T CAM can achieve 22.8% power reduction for the 4bits pre-comparison circuit All the simulation results are based on TSMC 0.13um CMOS technology and the clock frequency is 500MHz. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Low power pre-comparison scheme for NOR-type 10T content addressable memory | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 IEEE Asia Pacific Conference on Circuits and Systems | en_US |
dc.citation.spage | 1301 | en_US |
dc.citation.epage | 1304 | en_US |
dc.contributor.department | 友訊交大聯合研發中心 | zh_TW |
dc.contributor.department | D Link NCTU Joint Res Ctr | en_US |
dc.identifier.wosnumber | WOS:000246793200325 | - |
顯示於類別: | 會議論文 |