完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, MS | en_US |
dc.contributor.author | Lee, CL | en_US |
dc.contributor.author | Chang, YJ | en_US |
dc.contributor.author | Wu, WC | en_US |
dc.date.accessioned | 2014-12-08T15:25:18Z | - |
dc.date.available | 2014-12-08T15:25:18Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7695-2481-8 | en_US |
dc.identifier.issn | 1081-7735 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17686 | - |
dc.description.abstract | The crosstalk fault becomes more and more important in the deep submicron SoC and its detection involves sophisticated timing measurement. In this paper a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a critical width pulse, CWP to the victim line and detects the propagation of the CWP at the output of the victim line. The scheme is simple and simulation analysis and experiments show that it is effective in detecting crosstalk faults. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Crosstalk fault detection for interconnection lines based on path delay inertia principle | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | en_US |
dc.citation.spage | 106 | en_US |
dc.citation.epage | 111 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000236209400019 | - |
顯示於類別: | 會議論文 |