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dc.contributor.authorWu, MSen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChang, YJen_US
dc.contributor.authorWu, WCen_US
dc.date.accessioned2014-12-08T15:25:18Z-
dc.date.available2014-12-08T15:25:18Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7695-2481-8en_US
dc.identifier.issn1081-7735en_US
dc.identifier.urihttp://hdl.handle.net/11536/17686-
dc.description.abstractThe crosstalk fault becomes more and more important in the deep submicron SoC and its detection involves sophisticated timing measurement. In this paper a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. The scheme, without using timing measurement, applies a transition on the aggressor line and a critical width pulse, CWP to the victim line and detects the propagation of the CWP at the output of the victim line. The scheme is simple and simulation analysis and experiments show that it is effective in detecting crosstalk faults.en_US
dc.language.isoen_USen_US
dc.titleCrosstalk fault detection for interconnection lines based on path delay inertia principleen_US
dc.typeProceedings Paperen_US
dc.identifier.journal14TH ASIAN TEST SYMPOSIUM, PROCEEDINGSen_US
dc.citation.spage106en_US
dc.citation.epage111en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000236209400019-
顯示於類別:會議論文