Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region

Abstract

This paper investigates the Static Noise Margin (SNM) of FinFET SRAM cells operating in sub-threshold region using analytical solution of 3D Poisson's equation. An analytical SNM model for sub-threshold FinFET SRAM is demonstrated and validated by TCAD mixed-mode simulations. The stabilities of several novel independently controlled-gate FinFET SRAM cells are examined. Significant nominal RSNM improvements are observed in these novel cells. However, Write-ability is degraded and becomes an important concern for certain configurations in sub-threshold region. Our result indicates that R/W word-line (WL) voltage control technique is more effective than transistor sizing for improving the Write-ability of the FinFET sub-threshold SRAM. While 6T cell is not a viable candidate for sub-threshold SRAM and 8T/10T cells must be used in bulk CMOS, our analysis establishes the feasibility and viability of 6T FinFET cells for sub-threshold SRAM applications.