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dc.contributor.authorFan, Ming-Longen_US
dc.contributor.authorWu, Yu-Shengen_US
dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:25:21Z-
dc.date.available2014-12-08T15:25:21Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4256-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/17735-
dc.description.abstractThis paper investigates the Static Noise Margin (SNM) of FinFET SRAM cells operating in sub-threshold region using analytical solution of 3D Poisson's equation. An analytical SNM model for sub-threshold FinFET SRAM is demonstrated and validated by TCAD mixed-mode simulations. The stabilities of several novel independently controlled-gate FinFET SRAM cells are examined. Significant nominal RSNM improvements are observed in these novel cells. However, Write-ability is degraded and becomes an important concern for certain configurations in sub-threshold region. Our result indicates that R/W word-line (WL) voltage control technique is more effective than transistor sizing for improving the Write-ability of the FinFET sub-threshold SRAM. While 6T cell is not a viable candidate for sub-threshold SRAM and 8T/10T cells must be used in bulk CMOS, our analysis establishes the feasibility and viability of 6T FinFET cells for sub-threshold SRAM applications.en_US
dc.language.isoen_USen_US
dc.titleInvestigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Regionen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 IEEE INTERNATIONAL SOI CONFERENCEen_US
dc.citation.spage29en_US
dc.citation.epage30en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000276151400011-
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