Mechanism of on-current and off-current instabilities under electrical stress in polycrystalline silicon thin-film transistors

Abstract

The On-current (I(on)) and Off-current (I(off)) instabilities of polycrystalline silicon thin-film transistors (poly-Si TFTs) were investigated under various electrical stress conditions. The stress-induced device degradation was studied by measuring the dependences of I(on) and I(off) on the drain/gate voltages. Using this technique, dissimilar variations of I(on) and I(off) after stress were observed. The differences can be attributed to the variances in the amount of charges trapped in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. These results suggested a comprehensive model for the I(on) and I(off) instabilities of poly-Si TFTs.