標題: Pipelining technique for energy-aware datapaths
作者: Huang, WS
Lin, TJ
Ou, SH
Liu, CW
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: This paper presents a novel method to improve the energy awareness of the pipelined datapaths for varying throughputs. It activates the pipeline registers only when necessary; i.e. a data item can bypass the pipeline registers when the operation is free of race from the succeeding one, and when the glitch is minimal. Then, the clock pulses of the unused pipeline registers are gated to reduce the energy dissipation. Compared to the conventional clock gating approach, our proposed on-demand pipelining eliminates all redundant clock pulses whenever the peak datarate is not reached. Moreover, our method has a constant input-to-output latency for all operation modes, which significantly simplifies the integration tasks. In our simulations, the proposed on-demand pipelining saves up to 80% energy of conventional pipelined datapaths, and it can reduce about 34%-39% energy dissipation of those with gated-clock only.
URI: http://hdl.handle.net/11536/17760
ISBN: 0-7803-8834-8
ISSN: 0271-4302
期刊: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
起始頁: 1218
結束頁: 1221
Appears in Collections:Conferences Paper