完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yen, JH | en_US |
dc.contributor.author | Dung, LR | en_US |
dc.contributor.author | Shen, CY | en_US |
dc.date.accessioned | 2014-12-08T15:25:23Z | - |
dc.date.available | 2014-12-08T15:25:23Z | - |
dc.date.issued | 2005 | en_US |
dc.identifier.isbn | 0-7803-8834-8 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/17763 | - |
dc.description.abstract | A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Design of power-aware multiplier with graceful quality-power trade-offs | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | en_US |
dc.citation.spage | 1642 | en_US |
dc.citation.epage | 1645 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000232002401199 | - |
顯示於類別: | 會議論文 |