標題: Hierarchical instruction encoding for VLIW digital signal processors
作者: Liu, CH
Lin, TJ
Chao, CM
Hsiao, PC
Lin, LC
Chen, SK
Huang, CW
Liu, CW
Jen, CW
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2005
摘要: VLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.
URI: http://hdl.handle.net/11536/17782
ISBN: 0-7803-8834-8
ISSN: 0271-4302
期刊: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
起始頁: 3503
結束頁: 3506
Appears in Collections:Conferences Paper