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dc.contributor.authorChiang, THen_US
dc.contributor.authorDung, LRen_US
dc.contributor.authorYaung, MFen_US
dc.date.accessioned2014-12-08T15:25:24Z-
dc.date.available2014-12-08T15:25:24Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/17797-
dc.description.abstractFormal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.en_US
dc.language.isoen_USen_US
dc.titleModeling and formal verification of dataflow graph in system-level design using Petri neten_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.citation.spage5674en_US
dc.citation.epage5677en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000232002405081-
Appears in Collections:Conferences Paper