Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Jiang, TY	en_US
dc.contributor.author	Liu, CNJ	en_US
dc.contributor.author	Jou, JY	en_US
dc.date.accessioned	2014-12-08T15:25:24Z	-
dc.date.available	2014-12-08T15:25:24Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	0-7803-8834-8	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17798	-
dc.description.abstract	Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.	en_US
dc.language.iso	en_US	en_US
dc.title	Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS	en_US
dc.citation.spage	5682	en_US
dc.citation.epage	5685	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000232002405083	-
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