A low-power H.264/AVC decoder

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, TA	en_US
dc.contributor.author	Liu, TM	en_US
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:25:25Z	-
dc.date.available	2014-12-08T15:25:25Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	0-7803-9060-1	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17817	-
dc.description.abstract	In this paper, we can save memory access in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In our proposed hierarchical syntax parser, gated clock technique can be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.	en_US
dc.language.iso	en_US	en_US
dc.title	A low-power H.264/AVC decoder	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers	en_US
dc.citation.spage	283	en_US
dc.citation.epage	286	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000233985300073	-
顯示於類別：	會議論文