標題: Design of memory sub-system in H.264/AVC decoder
作者: Li, Chih-Hung
Chang, Chang-Hsuan
Peng, Wen-Hsiao
Hwang, Wei
Chiang, Tihao
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2007
摘要: In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency; less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
URI: http://hdl.handle.net/11536/9090
ISBN: 978-1-4244-0762-0
期刊: ICCE: 2007 DIGEST OF TECHNICAL PAPERS INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS
起始頁: 31
結束頁: 32
顯示於類別:會議論文