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dc.contributor.authorLi, YMen_US
dc.contributor.authorChou, HMen_US
dc.contributor.authorLee, BSen_US
dc.contributor.authorLu, CSen_US
dc.contributor.authorYu, SMen_US
dc.date.accessioned2014-12-08T15:25:34Z-
dc.date.available2014-12-08T15:25:34Z-
dc.date.issued2005en_US
dc.identifier.isbn4-9902762-0-5en_US
dc.identifier.urihttp://hdl.handle.net/11536/17965-
dc.description.abstractIn this paper, electrical characteristics of germanium (Ge) nanowire field effect transistors (FETs) are computationally investigated. A calibrated three-dimensional (3D) density-gradient simulation is performed to explore the electrical characteristics of Ge omega-shaped-gate FETs. The examined nanodevices are with a 70% gate coverage ratio. By evaluating the threshold voltage roll-off, the transfer characteristics, and the leakage current, our numerical results have shown that the Ge nanowire FET has potentially higher driving-capability than that of the silicon (Si) one. Due to good channel controllability of the omega-shaped-gate FET with the 70% gate coverage ratio, compared with the Si nanowire FET, the high mobility Ge nanowire FET significantly suppresses the effect of band-gap narrowing on the transport characteristics. Leakage current of the Ge nanowire FET depends upon the thickness of the gate channel film. A thinner Ge film leads to a lower leakage current. Preliminary numerical study on the Ge Nanowire FET with a propoer selection on gate material provides interesting results for the design and fabrication of high performance nanodevices in nanoelectronics era.en_US
dc.language.isoen_USen_US
dc.titleComputer simulation of germanium nanowire field effect transistorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journalSISPAD: 2005 International Conference on Simulation of Semiconductor Processes and Devicesen_US
dc.citation.spage227en_US
dc.citation.epage230en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000234260200056-
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