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dc.contributor.authorHsu, HCen_US
dc.contributor.authorChang, NYCen_US
dc.contributor.authorChang, TSen_US
dc.date.accessioned2014-12-08T15:25:38Z-
dc.date.available2014-12-08T15:25:38Z-
dc.date.issued2005en_US
dc.identifier.isbn0-7803-9060-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/18046-
dc.description.abstractHandling of the complexity which arises due the irregularity data nature for MPEG-4 object based video coding is an important issue in MPEG-4 texture decoder design. Another crucial issue is designing an efficient architecture to satisfy the resource sensitive nature of portable embedded video codec systems. This paper presents an architecture for texture decoding to address these two major issues. By adopting zero-skipping and zero index tables together, the throughput and power consumption are improved significantly. To avoid incurring extra hardware overhead, multiplication sharing and buffer sharing are also incorporated. ne synthesized design can perform texture decoding of CIF@30FPS under 2.18 MHz. using UMC 0.181 mu m 1P6M technology, the reported power consumption is 0.92 mW.en_US
dc.language.isoen_USen_US
dc.titleArchitecture design of MPEG-4 texture decoder - Supporting object-based video codingen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papersen_US
dc.citation.spage275en_US
dc.citation.epage278en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000233985300071-
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