Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Hsu, HC	en_US
dc.contributor.author	Chen, CM	en_US
dc.contributor.author	Ker, MD	en_US
dc.date.accessioned	2014-12-08T15:25:38Z	-
dc.date.available	2014-12-08T15:25:38Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	0-7803-9058-X	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18051	-
dc.description.abstract	NMOS with dummy-gate structure is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, the ESD current is discharged far away from the salicided surface channel of NMOS, therefore NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress.	en_US
dc.language.iso	en_US	en_US
dc.title	Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2005 IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI-TSA-TECH), Proceedings of Technical Papers	en_US
dc.citation.spage	19	en_US
dc.citation.epage	20	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000231405800006	-
顯示於類別：	會議論文