A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV

doi:10.1109/30.468017

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	CHEN, CL	en_US
dc.contributor.author	LIANG, BS	en_US
dc.contributor.author	JEN, CW	en_US
dc.date.accessioned	2014-12-08T15:03:15Z	-
dc.date.available	2014-12-08T15:03:15Z	-
dc.date.issued	1995-08-01	en_US
dc.identifier.issn	0098-3063	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/30.468017	en_US
dc.identifier.uri	http://hdl.handle.net/11536/1805	-
dc.description.abstract	A low-cost Raster Engine (RE) is designed and implemented to improve the performance of 3D computer graphics and image composition application for video games, multimedia PCs and interactive TVs. Three operation modes: Gouraud and Phong shading algorithms, and image composition are incorporated in this chip. Modified digital differential analyzer (DDA), 2-level pipeline, and constant execution time for calculating cos(n) theta are proposed as the features of this design. The accelerator is implemented by 0.8 um SPDM CMOS VLSI technology and able to release more then 50% CPU loads.	en_US
dc.language.iso	en_US	en_US
dc.title	A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/30.468017	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON CONSUMER ELECTRONICS	en_US
dc.citation.volume	41	en_US
dc.citation.issue	3	en_US
dc.citation.spage	724	en_US
dc.citation.epage	730	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1995TC78200050	-
dc.citation.woscount	3	-
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