A new method for extracting the channel-length reduction and the gate-voltage-dependent series resistance of counter-implanted p-MOSFET's

Abstract

Based on the channel-resistance measurement, a new method for extracting the channel-length reduction (Delta L-jj) and the gate-voltage-dependent source/drain resistance (R-SD) of counter-implanted p-MOSFET's is proposed, in which the necessity of the applying substrate bias is demonstrated and an empirical relationship between poly-Si gate length (L-M) and device structure parameters for Delta L-jj extraction is provided, This is the first attempt to extract the basic parameters of counter-implanted p-MOSFET's with the LDD structure, Numerical analysis using two-dimensional (2-D) device simulator has been used to verify the proposed extraction method, Furthermore, an improved approach to extract R-SD is also presented, Both numerical analysis and experimental results show good accuracy of our proposed method.