完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, WZen_US
dc.contributor.authorCheng, YLen_US
dc.contributor.authorLin, DSen_US
dc.date.accessioned2014-12-08T15:25:41Z-
dc.date.available2014-12-08T15:25:41Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8480-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/18102-
dc.description.abstractA fully integrated 10 Gbps optical receiver analog front-end, includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 mum CMOS technology. The receiver front-end provides a conversion gain up to 85 dBOmega and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is - 13 dBm at a bit-error rate of 10(-12) with 2(31)-1 pseudo-random bits. 3-D symmetric transformers are utilized in the AFE design for bandwidth enhancement.en_US
dc.language.isoen_USen_US
dc.titleA 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front enden_US
dc.typeProceedings Paperen_US
dc.identifier.journalESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCEen_US
dc.citation.spage263en_US
dc.citation.epage266en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000225412500057-
顯示於類別:會議論文