完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, GXen_US
dc.contributor.authorLee, CLen_US
dc.contributor.authorChen, JEen_US
dc.date.accessioned2014-12-08T15:25:45Z-
dc.date.available2014-12-08T15:25:45Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7695-2235-1en_US
dc.identifier.issn1081-7735en_US
dc.identifier.urihttp://hdl.handle.net/11536/18181-
dc.description.abstractIn this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.en_US
dc.language.isoen_USen_US
dc.titleA new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DACen_US
dc.typeProceedings Paperen_US
dc.identifier.journal13TH ASIAN TEST SYMPOSIUM, PROCEEDINGSen_US
dc.citation.spage58en_US
dc.citation.epage61en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000225878400010-
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