| 標題: | A 15b 20MS/s CMOS pipelined ADC with digital background calibration |
| 作者: | Liu, HC Lee, ZM Wu, JT 交大名義發表 National Chiao Tung University |
| 公開日期: | 2004 |
| URI: | http://hdl.handle.net/11536/18214 |
| ISBN: | 0-7803-8267-6 |
| ISSN: | 0193-6530 |
| 期刊: | 2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS |
| Volume: | 47 |
| 起始頁: | 454 |
| 結束頁: | 455 |
| 顯示於類別： | 會議論文 |
- 一個具備數位背景式校正機制之十三位元每秒一億次取樣0.18-um CMOS導管式類比數位轉換器的設計 / 劉議煌;Liu, Yi-Huang;洪浩喬;Hong, Hao-Chiao
- A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration / Liu, HC;Lee, ZM;Wu, JT
- A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps / Fang, Bing-Nan;Wu, Jieh-Tsorng
- A robust and fast digital background calibration technique for pipelined ADCs / Fan, Jen-Lin;Wang, Chung-Yi;Wu, Jieh-Tsorng
- 用於管道模式類比對數位轉換器的背景校準技術 / 劉鴻志;Hung Chih Liu;吳介琮;Jieh-Tsorng Wu
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