A novel fully self-aligned process for high cell density trench gate power MOSFETs

Abstract

A novel self-aligned process for high cell density trench gate power MOSFETs with only four mask layers was proposed. The specific on-resistance can be as low as 0.21 mOmega-cm(2) with 1.5um cell pitch and 35V breakdown voltage. Because this process shrinks trench space but not trench width, the quasi-saturation phenomenon is lighter. After optimization the thickness of n- drift layer and n+ substrate, specific on-resistance lower than 0.1 mOmega-cm(2) with 0.6um technology could be expected.