Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ker, MD | en_US |
dc.contributor.author | Hsu, KC | en_US |
dc.date.accessioned | 2014-12-08T15:25:56Z | - |
dc.date.available | 2014-12-08T15:25:56Z | - |
dc.date.issued | 2004 | en_US |
dc.identifier.isbn | 0-7803-8315-X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/18389 | - |
dc.description.abstract | A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-mum CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-mum CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | en_US |
dc.citation.spage | 381 | en_US |
dc.citation.epage | 386 | en_US |
dc.contributor.department | 電機學院 | zh_TW |
dc.contributor.department | College of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000222139900065 | - |
Appears in Collections: | Conferences Paper |