| 標題: | Initial-on ESD protection design with PMOS-triggered SCR device |
| 作者: | Ker, Ming-Dou Chen, Shih-Hung 電機學院 College of Electrical and Computer Engineering |
| 公開日期: | 2005 |
| 摘要: | A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-mu m CMOS process. |
| URI: | http://hdl.handle.net/11536/17991 http://dx.doi.org/10.1109/ASSCC.2005.251818 |
| ISBN: | 0-7803-9162-4 |
| DOI: | 10.1109/ASSCC.2005.251818 |
| 期刊: | 2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS |
| 起始頁: | 105 |
| 結束頁: | 108 |
| 顯示於類別： | 會議論文 |
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- Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-mu m CMOS technology / Chen, Shih-Hung;Ker, Ming-Dou
- Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection / Chen, Shih-Hung;Ker, Ming-Dou
- Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology / Ker, Ming-Dou;Chen, Shih-Hung
- SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes / Ker, MD;Hsu, KC
- A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's / Ker, MD;Chang, HH;Wu, CY
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