標題: | Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-mu m CMOS technology |
作者: | Chen, Shih-Hung Ker, Ming-Dou 電機學院 College of Electrical and Computer Engineering |
公開日期: | 2007 |
摘要: | PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, turned-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology. |
URI: | http://hdl.handle.net/11536/9679 |
ISBN: | 978-1-4244-1014-9 |
期刊: | IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS |
起始頁: | 245 |
結束頁: | 248 |
顯示於類別: | 會議論文 |