Initial-on ESD protection design with PMOS-triggered SCR device

doi:10.1109/ASSCC.2005.251818

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Chen, Shih-Hung	en_US
dc.date.accessioned	2014-12-08T15:25:35Z	-
dc.date.available	2014-12-08T15:25:35Z	-
dc.date.issued	2005	en_US
dc.identifier.isbn	0-7803-9162-4	en_US
dc.identifier.uri	http://hdl.handle.net/11536/17991	-
dc.identifier.uri	http://dx.doi.org/10.1109/ASSCC.2005.251818	en_US
dc.description.abstract	A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-mu m CMOS process.	en_US
dc.language.iso	en_US	en_US
dc.title	Initial-on ESD protection design with PMOS-triggered SCR device	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/ASSCC.2005.251818	en_US
dc.identifier.journal	2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS	en_US
dc.citation.spage	105	en_US
dc.citation.epage	108	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.identifier.wosnumber	WOS:000240872200027	-
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