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dc.contributor.authorKer, MDen_US
dc.contributor.authorHsu, KCen_US
dc.date.accessioned2014-12-08T15:25:56Z-
dc.date.available2014-12-08T15:25:56Z-
dc.date.issued2004en_US
dc.identifier.isbn0-7803-8315-Xen_US
dc.identifier.urihttp://hdl.handle.net/11536/18389-
dc.description.abstractA novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-mum CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and CDM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-mum CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.en_US
dc.language.isoen_USen_US
dc.titleNative-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuitsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGSen_US
dc.citation.spage381en_US
dc.citation.epage386en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000222139900065-
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