An efficient approach for error diagnosis in HDL design

Abstract

The growing of the modem design complexity leads the design error diagnosis to be a challenge for designers. In this paper, we propose an efficient approach for design error diagnosis automatically for designs in HDL. This approach can handle multiple errors occurring in a HDL design simultaneously with only one test case by analyzing the simulation outputs of the incorrect implementation. Furthermore, this approach reduces the error space by eliminating those statements that have no or lower possibility to become the error sources with retaining at least one error source in it. Hence, the effort spent on the debugging process can be greatly reduced.