A low power and high speed viterbi decoder chip for WLAN applications

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, CC	en_US
dc.contributor.author	Wu, CC	en_US
dc.contributor.author	Lee, CY	en_US
dc.date.accessioned	2014-12-08T15:26:12Z	-
dc.date.available	2014-12-08T15:26:12Z	-
dc.date.issued	2003	en_US
dc.identifier.isbn	0-7803-7995-0	en_US
dc.identifier.uri	http://hdl.handle.net/11536/18596	-
dc.description.abstract	This paper presents a 166Mb/s, 64-state, radix-4, 16-level soft decison Viterbi decoder for high speed WLAN applications. With the path merging and trace forward techniques, the memory read operations are reduced to save power cunsumption. A test chip is fabricated in 0.35 mum 1P4M CMOS process, and can achieve the maximum throughout rate of 166Mbit/s under 3.3V The measured power consumption is below 55mW under 66M6/s throughput rate at 2.2V.	en_US
dc.language.iso	en_US	en_US
dc.title	A low power and high speed viterbi decoder chip for WLAN applications	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE	en_US
dc.citation.spage	723	en_US
dc.citation.epage	726	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000189296900175	-
顯示於類別：	會議論文